1. Field of the Invention
A method of modifying the carrier mobility of a transistor is described. More specifically, the present invention describes a method of utilizing implants in a substrate to induce a mechanical stress in the substrate to modify the carrier mobility of a transistor.
2. Related Applications
Applications related to the present invention include: "Technique to Obtain Increased Channel Mobilities in NMOS Transistors by Gate Electrode Engineering", Ser. No. 09/340,954, filed Jun. 28, 1999, "Methodology for Control of Short Channel Effects in MOS Transistors", Ser. No. 09/342,0300, filed Jun. 28, 1999, and "Method for Reduced Capacitance Interconnect System Using Gaseous Implants into the ILD", Ser. No. 09/344,918, filed Jun. 28, 1999. Each of the related applications listed above has been assigned to the Assignee of the present invention.
3. Description of Related Art
FIG. 1 is a side cross-sectional view of an NMOS transistor 10 known in the art. A conventional transistor 10 generally includes a semiconductor generally comprising a silicon layer 16 having a source 20 and a drain 18 separated by a channel region 22. A thin oxide layer 14 separates a gate 12, generally comprising polysilicon, from the channel region 22. In the device 10 illustrated in FIG. 1, the source 20 and drain 18 are n+ regions having been doped by arsenic or phosphorous. The channel region 22 is generally boron doped. (Note that for both the source 20 and drain 18 regions and the channel region 22 other materials may also be used.) Fabrication of a transistor such as the device 10 illustrated in FIG. 1 is well-known in the art and will not be discussed in detail herein.
The speed or velocity (v) of the current through the channel region 22 is a function of the mobility (.mu.) of the channel region, as expressed by the formula v=.mu.E wherein E represents the electric field across the channel region 22. Because E is generally a constant value, the higher the carrier mobility (.mu.) of a device the faster the device can function. As the demand for faster devices continually grows in the industry, the desire for a device having an increased mobility also increases. Thus, a method for fabricating a device having an increased carrier mobility would be desirable.
Another issue that arises when dealing with transistors of the present art involves current leakage from the source to the drain. One of the limiting factors in the scaling of transistors to smaller dimensions is the inability of the gate to fully control the channel region below the gate. As the source and drain junctions approach one another, the lines of force resulting from the potential applied to the drain terminate on the source junction, causing Drain-induced Barrier Lowering (DIBL). This DIBL results in leakage current between the source and drain, and at short enough channel lengths, results in failure of the device. Thus, a method of reducing current leakage would allow for the fabrication of transistors fabricated on a smaller scale.